RTL Design Architect

Job Description Your Role Lead architecture, integration, and verification strategy for high-speed connectivity IPs and chiplet interconnect solutions. Define PCIe/CXL/ UCIe subsystem architecture. Drive protocol compliance strategy. Review integration architecture and performance requirements. Lead interoperability and compliance planning. Guide verification and validation teams. Interface directly with customer architects. Support roadmap and future standard adoption. Your Profile 12–20+ years in protocol/IP development. Deep expertise in PCIe Gen4/5/6. UCIe architecture expertise. Chiplet ecosystem experience. Strong knowledge of protocol stack and LTSSM. Experience with root complex, endpoint, switch architectures. Experience integrating PCIe into large SoCs. Strong architecture and verification background. Knowledge of SerDes architecture. What You'll Love About Working Here We value flexibility and support our employees with hybrid work options and adaptable schedules to maintain a healthy work-life balance. Our inclusive culture brings together diverse professionals committed to growth, innovation, and excellence. At Capgemini, you can work on cutting-edge projects in technology and engineering with industry leaders and contribute to innovative semiconductor solutions.